Learn
Learn — RTL design, verification, and tapeout
A curated set of technical primers to help RTL designers move from a clean simulation to a clean tapeout. Written by the team building ChipVerify AI, each guide focuses on the kind of failure modes that actually trip up real silicon projects: latch inference, width mismatches, blocking-vs-nonblocking races, clock domain crossing risks, and the open EDA tools — Yosys, Verilator, Verible — that the platform orchestrates under one verification loop.
Concepts
Concepts
Core ideas every RTL engineer should be fluent in before signoff.
RTL verification
What RTL verification covers and how lint, simulation, synthesis, and formal fit together.
/learn/rtl-verification
Clock domain crossing
Why CDC bugs survive simulation, and the synchronizer patterns that catch them.
/learn/clock-domain-crossing
Reset domain crossing (RDC)
Why an async reset that spans domains is its own hazard, and the reset synchronizer that fixes it.
/learn/reset-domain-crossing
Free CDC checker for Verilog
What a structural CDC checker flags, why lint and sim miss it, and how to scan your RTL free.
/learn/free-cdc-checker-verilog
Tapeout readiness
A practical checklist for taking RTL through lint, sim, synth, and formal before signoff.
/learn/tapeout-readiness
Logical equivalence checking (LEC)
What LEC really proves — combinational vs sequential, miters, k-induction, and why a proof over zero points is vacuous.
/learn/logical-equivalence-checking
Functional coverage closure
Code vs functional coverage, cross bins, and the false-100% traps — rounding, dropped crosses, and excluded nets.
/learn/functional-coverage-closure
DFT & scan-chain readiness
Scan rules for RTL — resetless flops, mixed posedge/negedge scan domains, lockup latches, and what structural DFT evidence shows.
/learn/dft-scan-readiness
SystemVerilog Assertions (SVA)
Immediate vs concurrent assertions, implication, sampled-value functions, and why a vacuous pass proves nothing.
/learn/systemverilog-assertions
Metastability & the two-flop synchronizer
How async crossings fail, MTBF intuition, and why a 2-FF synchronizer is single-bit only.
/learn/metastability
Setup & hold time and STA basics
Setup vs hold, the timing path, slack, WNS/TNS, and why setup fails slow while hold fails fast.
/learn/setup-hold-sta-basics
RTL lint checklist
A practical Verilog/SystemVerilog lint checklist — width, latches, sensitivity, drivers, dead logic, case completeness.
/learn/rtl-lint-checklist
FSM encoding: one-hot vs binary vs gray
2-block vs 3-block FSM style, encoding tradeoffs, and the default/parasitic/unreachable-state traps.
/learn/fsm-encoding
Low-power RTL & UPF basics
Power domains, isolation cells, level shifters, retention registers, and what static UPF checking can prove.
/learn/low-power-upf-basics
Synthesis vs simulation mismatch
Incomplete sensitivity lists, blocking-in-clocked, casex/casez, and full_case/parallel_case — the bugs that pass sim and fail in silicon.
/learn/synth-sim-mismatch
Reset & X-convergence
When a reset-less flop's power-up X reaches control or an output versus is structurally masked — and why X-prop sim is unsound.
/learn/reset-x-convergence
Timing-exception candidates
False-path and multicycle candidates with their assumptions, and why an unjustified exception silently hides a real timing violation.
/learn/timing-exception-candidates
Macro & wrapper contract checking
Cross-checking an RTL macro wrapper against the macro's Liberty/LEF pin contract — direction, width, and power/ground pins.
/learn/macro-contract-checking
UPF-vs-RTL isolation consistency
Unprotected power-domain crossings, missing level shifters, and isolation controls the UPF names but the RTL does not have.
/learn/upf-rtl-isolation-consistency
AXI4 & AXI4-Lite protocol basics
The five AXI channels, the VALID/READY handshake rule, bursts, and the common AMBA AXI protocol bugs.
/learn/axi4-protocol-basics
Verilog vs SystemVerilog
What SystemVerilog added — logic, always_comb/ff, enums, interfaces, assertions — and what's synthesizable.
/learn/verilog-vs-systemverilog
Synthesizable Verilog
What synthesizes and what doesn't, and how lint and synthesis catch non-synthesizable RTL early.
/learn/synthesizable-verilog
Implementation & open PDK
Implementation & open PDK
Taking verified RTL toward a physical layout on open process design kits — open-PDK preview, not foundry signoff.
Open-source RTL to GDSII (sky130)
The full open flow — Yosys, OpenROAD, KLayout — from Verilog to a sky130 GDSII layout, and what 'open-PDK preview' means.
/learn/rtl-to-gdsii-sky130
RISC-V core: pre-signoff evidence
Drop in the upstream SERV RV32I core and run lint, CDC, synth, sim, and the RVFI readiness scaffold on it — evidence, not ISA compliance; lockstep is a planned follow-up.
/learn/riscv-core-evidence
Integrating a RISC-V core (SERV vs Ibex)
A practical checklist for an upstream RISC-V core: choosing SERV vs Ibex, license and provenance, bus interfaces (Wishbone vs req/gnt/rvalid), assembling an APB SoC, and the evidence to run.
/learn/open-riscv-core-integration
Spike-vs-RTL lockstep co-simulation
What RVFI retire-trace comparison against a Spike reference model proves — bounded evidence for the executed program — and what it deliberately does not: ISA completeness or a signoff.
/learn/spike-rtl-lockstep
Common bugs
Common bugs
Failure modes our static analysis sees on real designs every week.
Inferred latches in Verilog
How combinational always blocks accidentally synthesize latches, and how to fix them.
/learn/inferred-latches-verilog
Output never assigned
Diagnosing module ports that never get a driver, and why lint catches what sim misses.
/learn/output-never-assigned
Blocking vs non-blocking
When to use = and <=, and the race conditions that follow when you mix them up.
/learn/blocking-vs-nonblocking
Width mismatches
Truncation, sign-extension, and zero-extension bugs the compiler will not warn about.
/learn/width-mismatch-verilog
Tools
Tools
The open EDA engines ChipVerify AI orchestrates — and how to use them well.
Yosys synthesis
An open synthesis flow for elaboration checks, gate-level netlists, and structure diagrams.
/learn/yosys-synthesis
Verilator simulation
Native-compiled Verilog simulation with coverage hooks and CI-friendly speed.
/learn/verilator-simulation
Verible lint
Google's open SystemVerilog lint and formatter for fast style and syntax feedback.
/learn/verible-lint
Closure & enterprise workflow
Closure & enterprise workflow
The plan, waiver, fix-loop, and visualization layer that turn a tool runner into a tapeout-readiness dashboard.
Verification waivers
Audit-trailed acceptance of known findings: rule, locator, reason, reviewer, expiry — and the anti-patterns that turn waivers into rubber-stamps.
/learn/verification-waivers
Auto-fix verify loop
A deterministic template patch is applied to an in-memory copy of the RTL, the static analyzer re-runs, and the issue delta is reported before a human applies the change.
/learn/auto-fix-verify
Waveform intelligence
A heuristic summary of a VCD trace — likely clocks, resets, signal groups, transaction markers, and warnings — without claiming a formal bus decode.
/learn/waveform-intelligence
Verification plan
The list of objectives a project has to meet before tapeout, each with status and owner, rolled up into a closure % the dashboard leads with.
/learn/verification-plan
Schematic issue highlighting
Mapping file-and-line findings onto the netlist so cells and wires light up where the bug is, not just where the source line is.
/learn/schematic-issue-highlighting
Tenant isolation
How ChipVerify AI keeps each tenant's RTL and results separate — request-scoped tenant context plus defense-in-depth PostgreSQL row-level security.
/learn/tenant-isolation
Run these checks on your own RTL
Sign in and ChipVerify AI runs the same open-source engines the guides reference (Verilator, Yosys, Verible, SymbiYosys) and returns pre-signoff evidence with file-and-line findings — structural analysis, not a foundry signoff.