- Always_comb
- SystemVerilog procedural block intended for combinational logic. The simulator and synthesis tools warn if any output is not assigned on every path, which prevents accidental latch inference. See: inferred latches.
- Always_ff
- SystemVerilog procedural block intended for sequential logic. Synthesis assumes a clocked flip-flop, and tools enforce that only non-blocking assignments are used inside. See: blocking vs non-blocking.
- Waveform intelligence
- A heuristic summary of a simulation trace: likely clocks and resets, signal groups, transaction markers, and advisory warnings. It helps navigate a large VCD; it does not score anomalies or grade the trace pass/fail. See: waveform intelligence.
- ASIC
- Application-Specific Integrated Circuit. A chip designed for one product or family, fabricated on a foundry process and committed to silicon at tapeout.
- Assertion
- A formal statement that a property holds during simulation or under formal proof. Catches bad behavior the moment it happens, instead of waiting for a downstream symptom.
- Blocking assignment
- Verilog procedural assignment using = that completes immediately. Appropriate inside combinational always blocks, but a common source of races when used in clocked logic. See: blocking vs non-blocking.
- CDC
- Clock Domain Crossing. Any signal whose source and destination flip-flops are clocked by unrelated clocks. Requires a synchronizer to control metastability. See: clock domain crossing.
- Closure %
- The percentage of a project's verification-plan objectives that are in 'covered' or 'waived' status. The single number that answers 'are we ready to tape out?' on a closure dashboard, computed from the tracked objective statuses. See: verification plan.
- Clock skew
- The difference in arrival time of the same clock edge at different flip-flops. Excessive skew causes hold-time and setup-time violations after place-and-route.
- Coverage
- In ChipVerify, code coverage measured by Verilator during simulation — line, branch, and (when enabled) toggle coverage. It reports which RTL constructs were exercised; it is not functional-coverage or signoff coverage.
- Equivalence checking
- A formal proof that two designs (typically pre- and post-synthesis, or before and after a refactor) implement the same Boolean function. Tools include Yosys EQY and commercial LEC.
- False path
- A timing path the designer asserts is never exercised at speed, so static timing analysis is told to ignore it (set_false_path). A tool can only suggest a candidate with the assumption it depends on; an unjustified false path silently hides a real violation. See: timing-exception candidates.
- FIFO
- First-In-First-Out buffer. The canonical building block for crossing clock domains or absorbing rate mismatches between producer and consumer.
- Flip-flop
- An edge-triggered storage element. The fundamental sequential primitive in synchronous digital design — every state bit in synthesizable RTL becomes a flip-flop.
- Formal verification
- Mathematically proving (or disproving) properties about a design without enumerating inputs. Bounded model checking and induction are the most common approaches. See: RTL verification.
- FPGA
- Field-Programmable Gate Array. A chip whose logic is configured after manufacturing, used for prototyping ASIC RTL and for production where volumes do not justify a full tapeout.
- FSM
- Finite State Machine. A controller described as states, transitions, and outputs. The most common RTL pattern for sequencing and protocol handling.
- GDS
- GDSII layout database — the geometric file the foundry uses to fabricate the chip. The artifact handed off at tapeout.
- Generate
- Verilog construct for parameterized structural elaboration: generate-for and generate-if produce different RTL based on parameters at compile time.
- Gray code
- A binary encoding where consecutive values differ in exactly one bit. Used for FIFO pointers crossing clock domains so the synchronizer never sees more than one bit change.
- HDL
- Hardware Description Language. The category that includes Verilog, SystemVerilog, and VHDL.
- Interface
- SystemVerilog construct that bundles signals and protocol logic into a single named entity. Reduces port-list churn when a bus signature changes.
- Isolation cell
- A cell on a power-domain crossing that clamps the net to a known value (0 or 1) while the source domain is powered down, driven by an isolation control signal. A UPF declares which strategy isolates which crossing. See: UPF-vs-RTL isolation consistency.
- Jitter
- Short-term variation in clock edge timing. Eats into the timing budget and can push borderline paths into hold or setup violations.
- Latch
- A level-sensitive storage element. Almost always inferred by mistake from an incomplete combinational always block, and a leading source of timing surprises. See: inferred latches.
- Level shifter
- A cell that translates signal levels at a crossing between power domains running at different voltages, so a low-voltage output is read correctly by a high-voltage input. A missing level shifter on a voltage crossing is a low-power intent gap. See: UPF-vs-RTL isolation consistency.
- Lint
- Static analysis of RTL for style, syntax, and obvious-bug patterns. Verible, Verilator-lint, and commercial linters all participate in this category. See: Verible lint.
- Lockstep co-simulation
- Running the same program on a reference model and on the design under test and comparing what each instruction did, in order. A passing run is bounded evidence that the core matched the reference for the executed program — not a proof of ISA completeness and not a signoff. See: Spike-vs-RTL lockstep.
- Metastability
- An unstable state a flip-flop enters when a setup/hold violation occurs at a clock edge. Resolves to 0 or 1 after a probabilistic delay — the reason synchronizers exist. See: clock domain crossing.
- Modport
- A SystemVerilog interface view that names which signals are inputs, outputs, or inouts for a particular module instance. Lets one interface serve multiple roles.
- MTBF
- Mean Time Between Failures. For synchronizers, the expected time between metastability events — a function of clock frequency, setup window, and synchronizer depth.
- Multicycle path
- A timing path the designer asserts has more than one clock period to settle (set_multicycle_path) — for example a flop gated by an enable that only asserts every N cycles. A tool can suggest a candidate with its assumption; the engineer must verify the period. See: timing-exception candidates.
- Non-blocking assignment
- Verilog procedural assignment using <= that schedules the right-hand side for the end of the time step. The correct choice for clocked logic. See: blocking vs non-blocking.
- Package
- SystemVerilog scope that exports types, parameters, and functions to multiple modules. The closest the language gets to a header file with namespacing.
- Parameter
- A compile-time constant supplied to a module. Used for widths, depths, and configuration choices that elaborate to fixed RTL per instance.
- PDK
- Process Design Kit. The foundry's collection of standard cells, design rules, models, and libraries needed to design for a specific manufacturing process.
- Race condition
- A simulation outcome that depends on the unspecified ordering of two events at the same time step. The reason blocking assignments in clocked logic are dangerous. See: blocking vs non-blocking.
- RDC
- Reset Domain Crossing. Analogous to CDC but for resets — when a flop in one reset domain feeds a flop in another, the asynchronous deassertion can corrupt state.
- Reference model
- An independent implementation of the same specification, used as the golden answer in co-simulation. For RISC-V, Spike (the official ISA simulator) is the reference. Comparing a design against a reference is only as strong as the reference is trustworthy and the stimulus is thorough. See: Spike-vs-RTL lockstep.
- Row-level security (RLS)
- A PostgreSQL feature that attaches a policy to a table so the database itself filters which rows a query can see, based on a runtime setting. ChipVerify binds the request's tenant id per transaction and the policy returns only that tenant's rows — a defense-in-depth backstop below the application's own tenant filtering. See: tenant isolation.
- RTL
- Register Transfer Level. The abstraction at which designers describe synchronous digital hardware as registers and the combinational logic between them. See: RTL verification.
- RVFI
- RISC-V Formal Interface. A standard per-instruction retire channel a core exposes when an instruction commits — valid, order, the instruction word, register reads/writes, the program counter, trap, and memory access. It is the contract riscv-formal proofs and reference-model lockstep compare against. See: Spike-vs-RTL lockstep.
- Schematic highlight
- A coloured overlay on a generated netlist schematic that maps a finding's source line and signal name to the corresponding cell or wire in the SVG. Lets engineers triage findings in the gate-level view they think in, not just the file:line view. See: schematic issue highlighting.
- Signoff
- The set of checks (timing, power, DRC, LVS, formal, coverage) that must pass before tapeout. Each check has a specific tool and an explicit criterion. See: tapeout readiness.
- Simulation
- Executing testbench stimulus against the design and observing outputs. Verilator and Icarus are the open-source workhorses. See: Verilator.
- SVA
- SystemVerilog Assertions. A property language for stating temporal correctness conditions, used in both simulation and formal flows.
- Synchronizer
- A small chain of flip-flops (usually two or three) inserted on a CDC path to absorb metastability. Standard practice for any single-bit signal crossing clock domains. See: clock domain crossing.
- Synthesis
- Translating RTL into a gate-level netlist using a target cell library. Yosys is the open-source tool ChipVerify AI orchestrates for this step. See: Yosys.
- Synth/sim mismatch
- RTL that means one thing to the simulator and another to the synthesis tool — incomplete sensitivity lists, blocking in clocked blocks, casex/casez, or full_case/parallel_case. The design passes a clean sim and the gates behave differently, with no testbench failure to chase. See: synthesis vs simulation mismatch.
- SystemVerilog
- An extension of Verilog with stronger types, classes, interfaces, assertions, and verification constructs. The dominant HDL for new designs and verification environments.
- Tapeout
- The point at which a design is committed to fabrication and the GDSII file is sent to the foundry. The checks that gate this step are collectively called signoff. See: tapeout readiness.
- Tinytapeout
- An open project that aggregates many small designs into a single shared tapeout, lowering the cost of getting custom silicon back. ChipVerify AI offers a free badge scanner for it.
- UVM
- Universal Verification Methodology. A SystemVerilog class library and methodology for building reusable, layered, constrained-random testbenches.
- Verification objective
- A single line item in a verification plan: a specific correctness, coverage, or process condition the project has agreed must be true at tapeout. Each objective has an owner, a category, evidence entries, and a status (planned, in_progress, covered, waived, or blocked) advanced through the API or UI. See: verification plan.
- Verilog
- The original Hardware Description Language for digital design, standardized by IEEE. Still widely used directly, and the substrate underneath SystemVerilog.
- Waiver
- An explicit, audit-trailed acceptance of a known finding before tapeout, recorded with rule_id, file/line, reason, reviewer, and an expires_at. Lets a team ship with documented residual risk without lowering the rule's noise floor. See: verification waivers.
- Width mismatch
- An assignment where the source and destination have different bit widths, leading to silent truncation or zero-extension. A leading cause of arithmetic bugs. See: width mismatches.
- Wishbone
- An open, royalty-free SoC bus standard with cyc/stb/we/ack handshaking. The native memory interface of several open cores (including SERV), commonly bridged into an APB or AXI fabric when integrating a core. See: open RISC-V core integration.
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