Open-Source RTL to GDSII on sky130: The Full Flow Explained

RTL-to-GDSII is the path that turns a Verilog or SystemVerilog design into the physical layout (a GDSII file) a foundry can fabricate. For decades that path required a six-figure commercial toolchain and an NDA-gated process design kit (PDK). The open-source flow built around Yosys, OpenROAD, and KLayout running on the SkyWater sky130 open PDK changed that: you can now take real RTL all the way to a manufacturable layout with tools anyone can install. This guide walks the stages, names the tool at each step, and is honest about where an open-PDK preview ends and a foundry signoff begins.

What sky130 is

sky130 is an open 130 nm process design kit, originally SkyWater’s SKY130 node, released with an open-source license so the standard-cell library, device models, and design rules are publicly available. That openness is what makes an end-to-end open flow possible: every stage, from synthesis through layout-versus-schematic, needs the same PDK data, and on a closed node that data sits behind a foundry NDA. gf180 (GlobalFoundries 180 nm) is a second open PDK with the same property. A 130 nm node is large by modern standards, but it is real silicon and an excellent target for learning, for low-volume and academic chips, and for shuttle programs such as Tiny Tapeout.

The stages, end to end

A modern open flow (OpenLane or the OpenROAD flow scripts, ORFS) runs these stages in order. Each consumes the previous stage’s output and the PDK.

Where verification meets implementation

Implementation is only as good as the RTL going in. Three pre-signoff checks pay for themselves before you ever start a place-and-route run. First, a clean synthesis pass: an inferred latch or a multi-driver net that survived simulation will produce a confusing netlist and unconstrained timing downstream. Second, CDC analysis: static timing analysis cannot reason about asynchronous crossings, so a missing synchronizer that reaches GDSII is a latent silicon bug, not a timing violation the router will catch. Third, logic equivalence between the synthesized netlist and the RTL, which proves the gate-level result actually matches the design you verified.

Signoff vs preview: the honest line

An open sky130 flow produces a real, manufacturable GDSII and a real set of DRC, LVS, and antenna reports. For sky130 and gf180 specifically, that output can be tapeout-grade because the decks are open. But running the same flow against a commercial node does not make you signed off on that node: foundry signoff requires the foundry’s qualified tools, qualified decks, and accountable sign-off, none of which the open stack can stand in for. The honest framing is: tapeout-grade evidence on open PDKs, and pre-signoff structural evidence everywhere else. See the tapeout readiness checklist for the full set of gates a submission has to clear.

How ChipVerify checks this

ChipVerify AI runs an open-PDK implementation flow on sky130 as a job: your RTL goes through Yosys synthesis, OpenROAD floorplan/place/CTS/route, and KLayout for GDSII and physical-verification reports, returning the layout plus DRC/LVS/antenna evidence. It also runs RTL-to-netlist logic equivalence with Yosys EQY so you can confirm the netlist matches the RTL. We describe this as an open-PDK implementation preview and pre-signoff evidence — not a foundry signoff and not a certification — because the accountable sign-off on a commercial node belongs to the foundry-qualified flow.

Related reading

• Yosys synthesis — the open synthesis engine that maps your RTL to sky130 cells.
• Tapeout readiness — the gates a design has to clear before any submission.
• RTL verification — the pre-implementation checks that keep your netlist sane.